Khanh's Research Group @ Univ. of Aizu

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    Verilog/SystemVerilog/VHDL tutorial
    
    Intro Intro
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    Coding Guidelines (Verilog HDL)
    
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    Clone the project
    
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  - ASIC
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    Place and Route
    
    Mini Ex
    
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    Explore the library
    
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    Post-synthesis simulation with timing
    
    Post-place-and-route sim
    
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    OpenRAM
    
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    Design: 🕸️ Network-on-Chip
    Design: 🕸️ Network-on-Chip
    
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    Power estimation
    
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    0. Installation
    
    Standalone RTL design
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    1. Create a project
    
    2. Run the project on FPGA
    
    3. Understand the reports
    
    Simple SoC
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    2. Port to SDK
    
    3. Run the program in the FPGA
    
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    Lab-4
    
    Lab-5
    
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    SNN on Basys 3
    
    SNN on Arty 7
    
    LIF neuron on MicroZed
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  - Spiking Neural Network
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    Introduction
    
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    Neuron
    
    Izhikevich
    
    SNNTorch
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    Official tutorial
    
    Bindsnet
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    Spiking Jelly
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    1.1 Time-step
    
    1.2 Using neuron
    
    1.3 Input size and net reset
    
    3.1 Revisit LIF neuron
    
    3.2 Revisit LIF neuron part 2
    
    3.3 Design your neuron
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Table of contents

Coding Guidelines (Verilog HDL)

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