Khanh's Research Group @ Univ. of Aizu

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    Verilog/SystemVerilog/VHDL tutorial
    
    Intro Intro
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    Coding Guidelines (Verilog HDL)
    
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    Clone the project
    
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    Place and Route
    
    Mini Ex
    
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    Post-synthesis simulation with timing
    
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    Design: 🕸️ Network-on-Chip
    Design: 🕸️ Network-on-Chip
    
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    0. Installation
    
    Standalone RTL design
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    1. Create a project
    
    2. Run the project on FPGA
    
    3. Understand the reports
    
    Simple SoC
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    2. Port to SDK
    
    3. Run the program in the FPGA
    
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    Lab-3
    
    Lab-4
    
    Lab-5
    
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    SNN on Basys 3
    
    SNN on Arty 7
    
    LIF neuron on MicroZed
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  - Spiking Neural Network
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    Introduction
    
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    Neuron
    
    Izhikevich
    
    SNNTorch
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    Official tutorial
    
    Bindsnet
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    Spiking Jelly
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    1.1 Time-step
    
    1.2 Using neuron
    
    1.3 Input size and net reset
    
    3.1 Revisit LIF neuron
    
    3.2 Revisit LIF neuron part 2
    
    3.3 Design your neuron
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Table of contents

Coding Guidelines (Verilog HDL)

aHYi7QDygBTzR5sh2GKhuw==;H4BhJAtIng2GLSwwDOL8q3XrmdECKVJuzda7+Ej8r39Rg0sD8oaylN9bqVcBl8km8dqWdU1yD/cW0HQSuVVWatDF15SwG473ttyDefIw7K6WYha7it1bk1EA6G2Z8ErJRD8Sejsyc4FxnJdXcLMGCGj6BOxL2nwqV+68OOhXtMOkVXrRS1qWyraJ1wmWp87Tn3CrmF5Cm0CJ+AF1x9l/Z4bZwoW9DRDjh0wQWw1MrqoU8rtvtWpN/3rKkvaYr0159GIiIl2zeZh/8r0201o10ycvT0TqgxzaNaTcrNFMMN2CY34i+0FPc1pCT22a023/9g8Z3vXIE4vnZ53hsIWJp8R0AkZQuc4VIJohaKT/hQI4Ds5qoxNH4BYw59r73ot1PL+1JLo68NW8yjH3+snjM7+q2BC7SqcYpGdb+ji3SqsUZssA82Z/oKBi2WqhSU9F5y1SnS4ByYdB82KlpaX7eikaMybyw539/bg7W4jNncFiLt9W2qx+7C7sycW/DZUXT6Ken786TXKLXbEb2TNxZNp21EpNZCK0pTHdGsIBLbOeIlajAPRhoYWfO6aGW1zO2p4xPcyA59A7mmjf0B+0yQznzPrsM3iD3Kv9Iy10Rp29V6lemp5Vz1zpa1mhw1lU+Qwq5kUKVWi90sqPU+31x2ikMbo40xgV5e197PCwYIhv0YUMtT5pJxJIrbGb4lvB98hn3b+VihjedFQVvVWovMpCJrTBYBLpClE2xy8OB+EUFCQGdt3nh3XrUd78iELw0TY9kVYxlbZDUMLYhXnA6+Lem1EQ59bLlWdp9PhY7o147Nqc/b61bMTj6tW/1u5DgnQMoZl+5j+3RVmt4LfMCb5Hh98TJQ9xvZAArgJucSw5BhKb0oVqVUv/XogOlTYKvtL9QSTTWAxggnAgRMtyzgV/kizYbv7ZxWllm3UEFoo=

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