Khanh's Research Group @ Univ. of Aizu

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ℹ️ Information
ℹ️ Information
- 🌐 About this website
- 🔰 Guidance for new student (AY 2025)
- 🔰 Checklist for new student orientation meeting
  🔰 Checklist for new student orientation meeting
- 🚂 Training for new members
  🚂 Training for new members
- 🔬 Server/Page Info
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- 📑 Paper submission
  📑 Paper submission
- 🎓 Graduation Thesis
  🎓 Graduation Thesis
  - Preparation
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👨‍🏫 Invited Talks
👨‍🏫 Invited Talks
📅 Meetings
📅 Meetings
🗂️ Tutorial
🗂️ Tutorial
- List of tutorials
- 🛠 HW Design
  🛠 HW Design
  - Verilog/SystemVerilog/VHDL tutorial
    Verilog/SystemVerilog/VHDL tutorial
    
    Intro
    
    Combinational Logic
    
    Sequential Logic
    
    Reset and Clock
    
    Naming
    
    RTL template
    
    Testbench template
    
    Useful website
    Useful website
    
    Asic-world
    
    Stitt-hub
    
    RTL-Training Repo
  - Simulate with Modelsim
    Simulate with Modelsim
    
    Introduction
    
    Clone the project
    
    Source the env variables
    
    Write your Verilog code
    
    Open Modelsim
    
    Use command line
    
    Code Coverage
    
    Write a script
    
    Learn More!
  - ASIC
    ASIC
    
    Basic
    Basic
    
    Getting started
    
    Writing Verilog
    
    RTL Simulation
    
    Synthesis (Synopsys DC)
    
    Place and Route
    
    Mini Ex
    
    Advanced
    Advanced
    
    Getting started
    
    Explore the library
    
    Post-synthesis simulation
    
    Post-synthesis simulation with timing
    
    Post-place-and-route sim
    
    Macro
    
    Through-Silicon-Via (TSV)
    
    OpenRAM
    
    Power estimation
    
    Clock-gating
    
    Temperature simulation
    
    Design: 🕸️ Network-on-Chip
    Design: 🕸️ Network-on-Chip
    
    Getting started
    
    Simulation
    
    SNN Simulation
    
    Synthesis
    
    Post-synthesis Simulation
    
    Place and Route
    
    Power estimation
    
    Sample projects
  - FPGA
    FPGA
    
    Basic
    Basic
    
    0. Installation
    
    Standalone RTL design
    Standalone RTL design
    
    1. Create a project
    
    2. Run the project on FPGA
    
    3. Understand the reports
    
    Simple SoC
    Simple SoC
    
    1. Create a project
    
    2. Port to SDK
    
    3. Run the program in the FPGA
    
    Custom IP
    Custom IP
    
    Introduction + Materials
    
    General Instruction
    
    Lab-1
    
    Lab-2
    
    Lab-3
    
    Lab-4
    
    Lab-5
    
    Sample Projects
    Sample Projects
    
    SNN on Basys 3
    
    SNN on Arty 7
    
    LIF neuron on MicroZed
- 🤖 Machine Learning
  🤖 Machine Learning
  - Getting started
  - General Machine Learning
    General Machine Learning
    
    Getting started
    
    Installation
    
    Dataset
    
    Notable techniques and Recommendation
  - Artificial Neural Network
  - Spiking Neural Network
    Spiking Neural Network
    
    Introduction
    
    Neurons
    
    Neurons
    
    Neuron
    
    Izhikevich
    
    SNNTorch
    SNNTorch
    
    Official tutorial
    
    Bindsnet
    Bindsnet
    
    STDP learning
    
    Spiking Jelly
    Spiking Jelly
    
    1.1 Time-step
    
    1.2 Using neuron
    
    1.3 Input size and net reset
    
    3.1 Revisit LIF neuron
    
    3.2 Revisit LIF neuron part 2
    
    3.3 Design your neuron
- Accessing servers
  Accessing servers
- 🎯 Optimization
  🎯 Optimization
  - Getting started
  - Single Objective
    Single Objective
    
    0-1 Knapsack
  - Multiple Objectives
    Multiple Objectives
    
    0-1 Knapsack
    
    MOO minicourse
- Makefile
  Makefile
- Git
  Git
  - Intro
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- Markdown
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♾️ Member
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  - AY2024
    
    AY2024
    
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🛂 Join Us
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🌐 Links
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- 📝 The Thinking Circuit
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📩 Contact

oiBrDbC8YGiKtg44bjDvcg==;kSg31MoGID1ax1yEcF1NAfLW7ao6inSZbPp1tb19/DpdStTiQM5/FNIfMnmSyb/7l1yiNdQn5ebbeuB/iMHB0SzEsuuNwry5euJejXmx5D+zD+zPgnheDPTivqfoFCFNMlwi3KMSd24LRFkq7QTJLE4hgioYtnyBbntUM/5IkEO6FaMJpeUXWrV7UEzvJd1zBOBRww0H4qndqsiqKK8sNuW6V8csZgTxqnD+L+g5M8/Fhr8r49OGMu7sGfRiPqwuKvUeE97Yl+0X3OCBtg/JRGqPwMZHv8N6jQmOTUtes0mHjoWO62FQb8D6NnuM0rD0fozsITZaJ5M/mroVhLc/qLPG/KY58rVttcJHNuK17IF7ASLgb+dcKJAS1Ms7bucFzio8NU9ljxhUJe7LJl8n+Ghw3UM6QSzjpXzbMTZQxrrCQO4iVe5IlAP3ok8OUbPc5lXQbPCRL/X+pH9jQ3De2sYDZfhOP77VkmVVaIMCF0KKKaoIsbLNLE+Ak33z9anPbST6Senqg3V5/ddUJBQbL2Ed2+NdO+yOSq4pbtKz2z6u3+re0KHHf/oHvbPSxAY61zDunwMdfCGuWLDOU9fAEzZG6J6Mb0Uhg1fCyG34ay86T7Uo1MlhDWrNPfDUwdnKUKRJDYGUc8uby2WryrZGUCVr1tyHA6kIMzkHUpxxpokm0G2Pp4TMv5EP5pM+fmMAKtEM3cdoR8rfqeD56Ua5xKbT5MqalGkbxDbh26hNfoBw4QeNo371JkFb1C5bFK1mt5XQg+CWQ94n6Rqm/JSfqgMTXVgDVnbINJwp/RECo4n/FMI+SYioG9rg8zGvz0BpsxJd3Jo5V2aneSi0w6UzRmFmRfCTkHptQsnleAfTBJgoey2qDdKq8cJ4nzR27zvNGjOcrIOxSYHcS/0FeD5sWJ2LBiEgqN6GWyvtXsWmPGRwv7+tEBsGcmjVL3WJUgSlvlBi2WKwYFqUXkAdbbt7LNj9HiMbl+9Pphuon5H1DgGFdfGFdxVB2g9PtL8j0tlRbparVcRZllsd1MsBEuEjlX6ZiR+rdy7kSXYoLwG+6+9fZvIFDsQ1jW6/c+vDqKtQxcV7QxDg+gIVR0563V3RUw7RPdAdbNCnYL0gndXxUdPLxT0cDeAAh7XOX7G8d+1K44u9J9JOiTZPXCXc6vKphQ==

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