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- 🌐 About this website
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  🔰 Checklist for new student orientation meeting
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🗂️ Tutorial
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- List of tutorials
- 🛠 HW Design
  🛠 HW Design
  - Verilog/SystemVerilog/VHDL tutorial
    Verilog/SystemVerilog/VHDL tutorial
    
    Intro
    
    Combinational Logic
    
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    Useful website
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  - Simulate with Modelsim
    Simulate with Modelsim
    
    Introduction
    
    Clone the project
    
    Source the env variables
    
    Write your Verilog code
    
    Open Modelsim
    
    Use command line
    
    Code Coverage
    
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    Learn More!
  - ASIC
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    Place and Route
    
    Mini Ex
    
    Advanced
    Advanced
    
    Getting started
    
    Explore the library
    
    Post-synthesis simulation
    
    Post-synthesis simulation with timing
    
    Post-place-and-route sim
    
    Macro
    
    Through-Silicon-Via (TSV)
    
    OpenRAM
    
    Power estimation
    
    Clock-gating
    
    Temperature simulation
    
    Design: 🕸️ Network-on-Chip
    Design: 🕸️ Network-on-Chip
    
    Getting started
    
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    Sample projects
  - FPGA
    FPGA
    
    Basic
    Basic
    
    0. Installation
    
    Standalone RTL design
    Standalone RTL design
    
    1. Create a project
    
    2. Run the project on FPGA
    
    3. Understand the reports
    
    Simple SoC
    Simple SoC
    
    1. Create a project
    
    2. Port to SDK
    
    3. Run the program in the FPGA
    
    Custom IP
    Custom IP
    
    Introduction + Materials
    
    General Instruction
    
    Lab-1
    
    Lab-2
    
    Lab-3
    
    Lab-4
    
    Lab-5
    
    Sample Projects
    Sample Projects
    
    SNN on Basys 3
    
    SNN on Arty 7
    
    LIF neuron on MicroZed
- 🤖 Machine Learning
  🤖 Machine Learning
  - Getting started
  - General Machine Learning
    General Machine Learning
    
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  - Artificial Neural Network
  - Spiking Neural Network
    Spiking Neural Network
    
    Introduction
    
    Neurons
    
    Neurons
    
    Neuron
    
    Izhikevich
    
    SNNTorch
    SNNTorch
    
    Official tutorial
    
    Bindsnet
    Bindsnet
    
    STDP learning
    
    Spiking Jelly
    Spiking Jelly
    
    1.1 Time-step
    
    1.2 Using neuron
    
    1.3 Input size and net reset
    
    3.1 Revisit LIF neuron
    
    3.2 Revisit LIF neuron part 2
    
    3.3 Design your neuron
- Accessing servers
  Accessing servers
- 🎯 Optimization
  🎯 Optimization
  - Getting started
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    Single Objective
    
    0-1 Knapsack
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    0-1 Knapsack
    
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🌐 Links
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📩 Contact

y07XkHoIDgO+9kR+T7VxTg==;GjyDyLZr1rWsFCwHPO4wwivZ0wen9/N4vPAQfrUwXihfm22+F08zaAUVggDzD2Zv387YjwyC+j3eSBxLp2C9c/ZCzVEkiWg7LE2QFtaQImKe6MejXqlmF0QR5DqAFOmXbR63nfVbXTOWxrZPH/uqZ5S0by3nckS+LVG5cINlu93H2XLQDxhNYOdYpYGF2bnmmyPp/Q/r7o/UqARa6lIKu0I31XxKS2zaHNLwPAxM9a0gCTiyV5eL/yFPdFCuBg62Yq/T0a8U9FYtXCjDK2sZsWV5pM5B74ZEzzrJ0PEs4yAhtrw9AEM3rAFVzteBtr4noqSz3YWOu027w+TPly1xx+YISEA2Wxp6CB7eK0a2makc/x5LEgts0Ycxw1eJipO9IygfokY0zqV5bZoZypdxuIEs8/VgPd+HkAa3HqaODN4WWodlARCUn9v3pFG2W2a0AOAwkTpF3IQGHxJXNZ9wG8n0vagTrSWJuq24bLc2bow=

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