Khanh's Research Group @ Univ. of Aizu

Research Paper Writing 1

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🗂️ Tutorial
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- List of tutorials
- 🛠 HW Design
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  - Verilog/SystemVerilog/VHDL tutorial
    Verilog/SystemVerilog/VHDL tutorial
    
    Intro
    
    Combinational Logic
    
    Sequential Logic
    
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    Useful website
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    Asic-world
    
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  - Simulate with Modelsim
    Simulate with Modelsim
    
    Introduction
    
    Clone the project
    
    Source the env variables
    
    Write your Verilog code
    
    Open Modelsim
    
    Use command line
    
    Code Coverage
    
    Write a script
    
    Learn More!
  - ASIC
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    Basic
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    Place and Route
    
    Mini Ex
    
    Advanced
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    Getting started
    
    Explore the library
    
    Post-synthesis simulation
    
    Post-synthesis simulation with timing
    
    Post-place-and-route sim
    
    Macro
    
    Through-Silicon-Via (TSV)
    
    OpenRAM
    
    Power estimation
    
    Clock-gating
    
    Temperature simulation
    
    Design: 🕸️ Network-on-Chip
    Design: 🕸️ Network-on-Chip
    
    Getting started
    
    Simulation
    
    SNN Simulation
    
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    Sample projects
  - FPGA
    FPGA
    
    Basic
    Basic
    
    0. Installation
    
    Standalone RTL design
    Standalone RTL design
    
    1. Create a project
    
    2. Run the project on FPGA
    
    3. Understand the reports
    
    Simple SoC
    Simple SoC
    
    1. Create a project
    
    2. Port to SDK
    
    3. Run the program in the FPGA
    
    Custom IP
    Custom IP
    
    Introduction + Materials
    
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    Lab-1
    
    Lab-2
    
    Lab-3
    
    Lab-4
    
    Lab-5
    
    Sample Projects
    Sample Projects
    
    SNN on Basys 3
    
    SNN on Arty 7
    
    LIF neuron on MicroZed
- 🤖 Machine Learning
  🤖 Machine Learning
  - Getting started
  - General Machine Learning
    General Machine Learning
    
    Getting started
    
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    Notable techniques and Recommendation
  - Artificial Neural Network
  - Spiking Neural Network
    Spiking Neural Network
    
    Introduction
    
    Neurons
    
    Neurons
    
    Neuron
    
    Izhikevich
    
    SNNTorch
    SNNTorch
    
    Official tutorial
    
    Bindsnet
    Bindsnet
    
    STDP learning
    
    Spiking Jelly
    Spiking Jelly
    
    1.1 Time-step
    
    1.2 Using neuron
    
    1.3 Input size and net reset
    
    3.1 Revisit LIF neuron
    
    3.2 Revisit LIF neuron part 2
    
    3.3 Design your neuron
- Accessing servers
  Accessing servers
- 🎯 Optimization
  🎯 Optimization
  - Getting started
  - Single Objective
    Single Objective
    
    0-1 Knapsack
  - Multiple Objectives
    Multiple Objectives
    
    0-1 Knapsack
    
    MOO minicourse
- Makefile
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HtpzMJpW33v/yemH5xoMDw==;cUHXrerI12wHAbAFCo/Slx9CPqLCvTXj8UxTciIs/u8vwGjsII2q2eZ8lNdvjXX/6rjdnhnwB4eviuINkSyyQD7OpXtXPFLht6mtLGACWADdynd+KcyMsY64s/GBfOHsyufGutSCTNQAyZjWv3TD65pgaHyv+X0U1MWdawtLTUx9BXC1KsG9UQZDctaST0Ps8gj3sWxQz7807dskRTiEk8rzVHXIoehXnGNLqot9kQKBsJGpe7O37sar4A1Buq0P0iadKivNYINybezro35bFL34heYz1IDUPh/JM0D/lxW81fBHW1MT4/JV52T6atU0Us96Xr42Aax05y1z9ju+5r/+iuEIysR9qS5qeZmT5+psW5G0HSUPjh/+dYSEkyBX57cgPBoV3/gx0NIEIgqKAHNlC2Hq/wG9La7bMHYSvLFr667uvqNn7M7LlQb98AGjYUPyhFAfqN2/o0UTtwJ2bQo2GTF9jmIaKRm+FEEFql+9CK0vI5TEkA4/nmDCr3BjcYS1OsWo/AjPkmyr/sxjmKJe3Jo+vhVbnatzp8vMkgLIlBZq/4SKZDvPGIhak3UtaZMN/eaGl5J1XWw7gbdot+SdCjrHN24z/0032V89cGWadf7CoPQ1votkVacrc7UzMcAUYyjC73N+AWJioX0m022XAv46PeJPgIWmGYpB/tEbw2rrVxlQNjGCpdUz4/Fi+kJQR7QK6yM6Wig2UWfmbttPH2GElGEYAocq+bJD5DY3nqAx4k82z0El+z/+8afojr4mblPrWnwp/KKVxWHE5gODwrdkzG5HUk1zIU1RWWT9wieFW8dhzi/hiGLZwYvS+71SVZKFOyZtucEa7LN/QmiPxB3/v+2uf+yOY/udUkSk0/NvPBti1r6rGeg9NohXrshHCGo77vJ05btW5xDfmVz1mnTD2aiRxGrc3j+TEDms7BYD/uw+UKe/AldcVMXLJL8ACqFwU3fa/4Li+JKLPNZaL79uZUtE4jCFO5UBHGXmpwWpeXxA8GAfNachYUu839mRF4rhIxZrczNq/B7RXxs391Utw3xBvgtTS1rChRzRW8IevVwHzK2imsKgYjuyYCtrtQ2OYMNo0MD+btfxyZsgrhAnAQIY8mhJCt9TiWf/sUsLZ/D54tVhft6DC3v1iX3tSaGg11NqQFI0l596WJxEtXHlIj1QuxAMthEipbB3Z1LKxBWIPphhfMr2iix8

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