Khanh's Research Group @ Univ. of Aizu

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    Verilog/SystemVerilog/VHDL tutorial
    
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  - Simulate with Modelsim
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  - ASIC
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    Place and Route
    
    Mini Ex
    
    Advanced
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    Getting started
    
    Explore the library
    
    Post-synthesis simulation
    
    Post-synthesis simulation with timing
    
    Post-place-and-route sim
    
    Macro
    
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    OpenRAM
    
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    Design: 🕸️ Network-on-Chip
    Design: 🕸️ Network-on-Chip
    
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    SNN Simulation
    
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  - FPGA
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    Basic
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    0. Installation
    
    Standalone RTL design
    Standalone RTL design
    
    1. Create a project
    
    2. Run the project on FPGA
    
    3. Understand the reports
    
    Simple SoC
    Simple SoC
    
    1. Create a project
    
    2. Port to SDK
    
    3. Run the program in the FPGA
    
    Custom IP
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    Lab-3
    
    Lab-4
    
    Lab-5
    
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    SNN on Basys 3
    
    SNN on Arty 7
    
    LIF neuron on MicroZed
- 🤖 Machine Learning
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  - General Machine Learning
    General Machine Learning
    
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  - Artificial Neural Network
  - Spiking Neural Network
    Spiking Neural Network
    
    Introduction
    
    Neurons
    
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    Neuron
    
    Izhikevich
    
    SNNTorch
    SNNTorch
    
    Official tutorial
    
    Bindsnet
    Bindsnet
    
    STDP learning
    
    Spiking Jelly
    Spiking Jelly
    
    1.1 Time-step
    
    1.2 Using neuron
    
    1.3 Input size and net reset
    
    3.1 Revisit LIF neuron
    
    3.2 Revisit LIF neuron part 2
    
    3.3 Design your neuron
- Accessing servers
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- 🎯 Optimization
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    0-1 Knapsack
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    0-1 Knapsack
    
    MOO minicourse
- Makefile
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    Recommended tutorial
    
    How to solve merge conflicts
    
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Table of contents

Recommended tutorial
How to solve merge conflicts
Other tutorials

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