web-int@klab-aizu

Introduction

Initializing search

🏠 Home
ℹ️ Information
ℹ️ Information
- 🌐 About this website
- 🔰 Guidance for new student (AY 2025)
- 🔰 Checklist for new student orientation meeting
  🔰 Checklist for new student orientation meeting
- 🚂 Training for new members
  🚂 Training for new members
- 🔬 Server/Page Info
  🔬 Server/Page Info
- 📑 Paper submission
  📑 Paper submission
- 🎓 Graduation Thesis
  🎓 Graduation Thesis
  - Preparation
  - After the presentation
👨‍🏫 Invited Talks
👨‍🏫 Invited Talks
📅 Meetings
📅 Meetings
🗂️ Tutorial
🗂️ Tutorial
- List of tutorials
- 🛠 HW Design
  🛠 HW Design
  - Verilog/SystemVerilog/VHDL tutorial
    Verilog/SystemVerilog/VHDL tutorial
    
    Intro
    
    Combinational Logic
    
    Sequential Logic
    
    Reset and Clock
    
    Naming
    
    RTL template
    
    Testbench template
    
    Useful website
    Useful website
    
    Asic-world
    
    Stitt-hub
    
    RTL-Training Repo
  - Simulate with Modelsim
    Simulate with Modelsim
    
    Introduction
    
    Clone the project
    
    Source the env variables
    
    Write your Verilog code
    
    Open Modelsim
    
    Use command line
    
    Code Coverage
    
    Write a script
    
    Learn More!
  - ASIC
    ASIC
    
    Basic
    Basic
    
    Getting started
    
    Writing Verilog
    
    RTL Simulation
    
    Synthesis (Synopsys DC)
    
    Place and Route
    
    Mini Ex
    
    Advanced
    Advanced
    
    Getting started
    
    Explore the library
    
    Post-synthesis simulation
    
    Post-synthesis simulation with timing
    
    Post-place-and-route sim
    
    Macro
    
    Through-Silicon-Via (TSV)
    
    OpenRAM
    
    Power estimation
    
    Clock-gating
    
    Temperature simulation
    
    Design: 🕸️ Network-on-Chip
    Design: 🕸️ Network-on-Chip
    
    Getting started
    
    Simulation
    
    SNN Simulation
    
    Synthesis
    
    Post-synthesis Simulation
    
    Place and Route
    
    Power estimation
    
    Sample projects
  - FPGA
    FPGA
    
    Basic
    Basic
    
    0. Installation
    
    Standalone RTL design
    Standalone RTL design
    
    1. Create a project
    
    2. Run the project on FPGA
    
    3. Understand the reports
    
    Simple SoC
    Simple SoC
    
    1. Create a project
    
    2. Port to SDK
    
    3. Run the program in the FPGA
    
    Custom IP
    Custom IP
    
    Introduction + Materials
    
    General Instruction
    
    Lab-1
    
    Lab-2
    
    Lab-3
    
    Lab-4
    
    Lab-5
    
    Sample Projects
    Sample Projects
    
    SNN on Basys 3
    
    SNN on Arty 7
    
    LIF neuron on MicroZed
- 🤖 Machine Learning
  🤖 Machine Learning
  - Getting started
  - General Machine Learning
    General Machine Learning
    
    Getting started
    
    Installation
    
    Dataset
    
    Notable techniques and Recommendation
  - Artificial Neural Network
  - Spiking Neural Network
    Spiking Neural Network
    
    Introduction
    
    Neurons
    
    Neurons
    
    Neuron
    
    Izhikevich
    
    SNNTorch
    SNNTorch
    
    Official tutorial
    
    Bindsnet
    Bindsnet
    
    STDP learning
    
    Spiking Jelly
    Spiking Jelly
    
    1.1 Time-step
    
    1.2 Using neuron
    
    1.3 Input size and net reset
    
    3.1 Revisit LIF neuron
    
    3.2 Revisit LIF neuron part 2
    
    3.3 Design your neuron
- Accessing servers
  Accessing servers
- 🎯 Optimization
  🎯 Optimization
  - Getting started
  - Single Objective
    Single Objective
    
    0-1 Knapsack
  - Multiple Objectives
    Multiple Objectives
    
    0-1 Knapsack
    
    MOO minicourse
- Makefile
  Makefile
- Git
  Git
  - Intro
  - Basic
  - Advanced
  - Branch
- Markdown
  Markdown
  - Intro
  - Basic
  - Advanced
♾️ Member
♾️ Member
- Faculty Advisor
  Faculty Advisor
- Graduate
  Graduate
- Undergraduate
  Undergraduate
- Exchange Student
  Exchange Student
  - AY2024
    
    AY2024
- Alumni
  Alumni
  - AY2023
    
    AY2023
    
    NGUYEN Ngo Doanh
  - AY2024
    
    AY2024
    
    SHIOTA Rui
    
    KOBAYASHI Ryoji
    
    HANYU Yuga
🎗️ Management
🎗️ Management
- 🔒 Password Protected
- 🖥️ Devices
- 📚 Books
- 🌐 Website
- 🖥 Server: how-to
- ⚗️ Materials
  ⚗️ Materials
- 🈸 University Docs
  🈸 University Docs
🖼️ Moments
🖼️ Moments
- Archive
  Archive
- Categories
  Categories
  - Conference
  - Exhibition
  - Graduation
  - Interview
  - Lecture
  - Master
  - News
  - Travel
  - Undergraduate
🎟️ Events
🎟️ Events
🛂 Join Us
🛂 Join Us
- For undergraduate students
- For postgraduate candidates
- Scholarships
- TA/RA/Part-time Positions
- How to write a research plan
- How we work
- What you learn
- GT themes (for B2 students)
  GT themes (for B2 students)
  - AY2025
  - AY2024
  - AY2023
  - AY2022
- Alumni Voices
🌐 Links
🌐 Links
- 📝 The Thinking Circuit
- 🚧 Project
  🚧 Project
  - Torch2HW
  - 🎓 Available GT Topics (2024)
- 🌐 Useful link
- ↗️ Github
- ▶️ YouTube
📩 Contact

mWjYBxnhL9bnA8EExpi5ag==;8C6p6J/m/havotZaP0TwzbixX4NuokbRaa720IqkVQTfkyxanCweyQt7EFBzyKwcnmnkMCDcw1/UfZeEjXmnM8HZhev1b7tRxTRnFmgfexfroR/z9CKeKhFWyadMvOhrhrBBSOx62OFUQo0C6/RWqlhZDt9a2+ToP0lxXDmlZK3pWtEdu+6XBYiZ27IQT+/qEn4bSdOygoPFljAhpRkzlBb8QzkxdxJxYOHRkH9niBviE5JEPxwHmG6AYQIzc1YwwacoMkmx/0tvIqdtgVDsmRGxJHiYPcavXyY3N6ZppEVOXcKiEHH5++JhZkMuPcVbKAF8OJ5S2Gyt7lyYUPnQkdBPui7IKev/hji5uh4/y6ZBifGURh7WM0RvZoP6eY5492JngNrqJmPfD0OVfImU0xuB6D6zq6er9uMygw2QLXHNHnPm7zzcq4lCAXnOox4SqQVpBDZGrGti5EESGmuSzPk200cxlpWB93Ez1iNjg6s4NTMzNHN6fDYMVbZp7DAjVAznuOK9/cf+uId5Ytiwe2AbmlI7MbNxIHDDIKTG+Nc5yfEdUsKkJBQDAOthjFSZvc6GRlECjTK4LQvfpnAhnyVLTC6hV7riziOCJK3kPIzCL/XU4vGTdTvbqlElEk3TRVb6d/iyrmvGHHaowK4I7d5a9iIr95hUQdq+eec40CY=

㊙️ This website is password-protected and accessible to authorized members only.

Contact your administrator for access to this page.