Khanh's Research Group @ Univ. of Aizu

Introduction

🏠 Home
ℹ️ Information
ℹ️ Information
- 🌐 About this website
- 🔰 Guidance for new student (AY 2026)
- 🔰 Checklist for new student orientation meeting
  🔰 Checklist for new student orientation meeting
- 🚂 Training for new members
  🚂 Training for new members
- 🔬 Server/Page Info
  🔬 Server/Page Info
- 📑 Paper submission
  📑 Paper submission
- 🎓 Graduation Thesis
  🎓 Graduation Thesis
  - Preparation
  - After the presentation
👨‍🏫 Invited Talks
👨‍🏫 Invited Talks
📅 Meetings
📅 Meetings
🗂️ Tutorial
🗂️ Tutorial
- List of tutorials
- 🛠 HW Design
  🛠 HW Design
  - Verilog/SystemVerilog/VHDL tutorial
    Verilog/SystemVerilog/VHDL tutorial
    
    Intro
    
    Combinational Logic
    
    Sequential Logic
    
    Reset and Clock
    
    Naming
    
    RTL template
    
    Testbench template
    
    Useful website
    Useful website
    
    Asic-world
    
    Stitt-hub
    
    RTL-Training Repo
  - Simulate with Modelsim
    Simulate with Modelsim
    
    Introduction
    
    Clone the project
    
    Source the env variables
    
    Write your Verilog code
    
    Open Modelsim
    
    Use command line
    
    Code Coverage
    
    Write a script
    
    Learn More!
  - ASIC
    ASIC
    
    Basic
    Basic
    
    Getting started
    
    Writing Verilog
    
    RTL Simulation
    
    Synthesis (Synopsys DC)
    
    Place and Route
    
    Mini Ex
    
    Advanced
    Advanced
    
    Getting started
    
    Explore the library
    
    Post-synthesis simulation
    
    Post-synthesis simulation with timing
    
    Post-place-and-route sim
    
    Macro
    
    Through-Silicon-Via (TSV)
    
    OpenRAM
    
    Power estimation
    
    Clock-gating
    
    Temperature simulation
    
    Design: 🕸️ Network-on-Chip
    Design: 🕸️ Network-on-Chip
    
    Getting started
    
    Simulation
    
    SNN Simulation
    
    Synthesis
    
    Post-synthesis Simulation
    
    Place and Route
    
    Power estimation
    
    Sample projects
  - FPGA
    FPGA
    
    Basic
    Basic
    
    0. Installation
    
    Standalone RTL design
    Standalone RTL design
    
    1. Create a project
    
    2. Run the project on FPGA
    
    3. Understand the reports
    
    Simple SoC
    Simple SoC
    
    1. Create a project
    
    2. Port to SDK
    
    3. Run the program in the FPGA
    
    Custom IP
    Custom IP
    
    Introduction + Materials
    
    General Instruction
    
    Lab-1
    
    Lab-2
    
    Lab-3
    
    Lab-4
    
    Lab-5
    
    Sample Projects
    Sample Projects
    
    SNN on Basys 3
    
    SNN on Arty 7
    
    LIF neuron on MicroZed
- 🤖 Machine Learning
  🤖 Machine Learning
  - Getting started
  - General Machine Learning
    General Machine Learning
    
    Getting started
    
    Installation
    
    Dataset
    
    Notable techniques and Recommendation
  - Artificial Neural Network
  - Spiking Neural Network
    Spiking Neural Network
    
    Introduction
    
    Neurons
    
    Neurons
    
    Neuron
    
    Izhikevich
    
    SNNTorch
    SNNTorch
    
    Official tutorial
    
    Bindsnet
    Bindsnet
    
    STDP learning
    
    Spiking Jelly
    Spiking Jelly
    
    1.1 Time-step
    
    1.2 Using neuron
    
    1.3 Input size and net reset
    
    3.1 Revisit LIF neuron
    
    3.2 Revisit LIF neuron part 2
    
    3.3 Design your neuron
- Accessing servers
  Accessing servers
- 🎯 Optimization
  🎯 Optimization
  - Getting started
  - Single Objective
    Single Objective
    
    0-1 Knapsack
  - Multiple Objectives
    Multiple Objectives
    
    0-1 Knapsack
    
    MOO minicourse
- Makefile
  Makefile
- Git
  Git
  - Intro
  - Basic
  - Advanced
  - Branch
- Markdown
  Markdown
  - Intro
  - Basic
  - Advanced
♾️ Member
♾️ Member
- Faculty Advisor
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- Graduate
  Graduate
- Undergraduate
  Undergraduate
- Exchange Student
  Exchange Student
  - AY2024
    
    AY2024
- Alumni
  Alumni
  - AY2025
    
    AY2025
  - AY2024
    
    AY2024
    
    SHIOTA Rui
    
    KOBAYASHI Ryoji
    
    HANYU Yuga
  - AY2023
    
    AY2023
    
    NGUYEN Ngo Doanh
🎗️ Management
🎗️ Management
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🖼️ Moments
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- Archive
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🎟️ Events
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⚔️ Students' Activities
⚔️ Students' Activities
- Awards
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  - All Contests
  - IEEE CAS Society Design Contest
    
    IEEE CAS Society Design Contest
  - LSI Contest
    
    LSI Contest
🛂 Join Us
🛂 Join Us
- For undergraduate students
- For postgraduate candidates
- Scholarships
- TA/RA/Part-time Positions
- How to write a research plan
- How we work
- What you learn
- GT themes (for B2 students)
  GT themes (for B2 students)
  - AY2025
  - AY2024
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  - AY2022
- Alumni Voices
🌐 Links
🌐 Links
- 📝 The Thinking Circuit
- 🚧 Project
  🚧 Project
  - Torch2HW
  - 🎓 Available GT Topics (2024)
- 🌐 Useful link
- ↗️ Github
- ▶️ YouTube
📩 Contact

HCmuBWtSjuSw/hMz9EecJg==;7UEuKLFzrjGBB3LKhHW+j1febHdj0C1juGwnlGpTwwCotUKi7VAUuiwmhgoMWVEB9JqITUYXXoOgQsybVqRJuukaHK0fmBu2yw/k4yt4K0aN3wgpha9ORFFKABd1+LGnR1BmE1llZtdEEnCTGa1xdbrC4bd7X0eQbxuUaxLRe2SsY36qmRh6QDdAdY7Ln7kFL65PQflPOeHMqJPxVj9ckUtfflZZZimnxsdJagUBasWAoSwaPlFFxlM2gfdAOYPZ3YVqM+ERCWqAsDHQraogF9FQ2FRSKSn0NSokC5xOxegJRbrOi7CH3AQ0m3vlavU8iIYalJLdBpYJ+WJJwkzJbpJt4I1WCEPKaFQazBNLDl1ID4TVPJbF3fex9jUPOrAttFsf8N0X7H+XMaV8KMDBOLO1lrwGp00Hi2hpZttX80/uWsU5EZI3K3dfuzPS73L5E5/l5w1AkV3LuEGg986edleDoaz6rfX+zXNahadcVIuEEntZjcGjxr1n9QQQoY5MyP/jjGuDLMptxRKUsWE6cHk2dpIBeY5Yxr4V56xvheIrABM4BfmeZ+k/m9ac09GjIDmawXbL1JJ8EvoAk0FFZOAJnWuYdteUtaFCf5OjKxCZWT50LT+t0WFjMA54cArseFzesld3qcN4fQ9MnzBRKL/H+KNDUQj79yZTMuHtle4=

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