Khanh's Research Group @ Univ. of Aizu

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  - Simulate with Modelsim
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    Clone the project
    
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  - ASIC
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    Design: 🕸️ Network-on-Chip
    Design: 🕸️ Network-on-Chip
    
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  - FPGA
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    Basic
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    0. Installation
    
    Standalone RTL design
    Standalone RTL design
    
    1. Create a project
    
    2. Run the project on FPGA
    
    3. Understand the reports
    
    Simple SoC
    Simple SoC
    
    1. Create a project
    
    2. Port to SDK
    
    3. Run the program in the FPGA
    
    Custom IP
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    SNN on Basys 3
    
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- 🤖 Machine Learning
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  - General Machine Learning
    General Machine Learning
    
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  - Artificial Neural Network
  - Spiking Neural Network
    Spiking Neural Network
    
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    Neuron
    
    Izhikevich
    
    SNNTorch
    SNNTorch
    
    Official tutorial
    
    Bindsnet
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    STDP learning
    
    Spiking Jelly
    Spiking Jelly
    
    1.1 Time-step
    
    1.2 Using neuron
    
    1.3 Input size and net reset
    
    3.1 Revisit LIF neuron
    
    3.2 Revisit LIF neuron part 2
    
    3.3 Design your neuron
- Accessing servers
  Accessing servers
- 🎯 Optimization
  🎯 Optimization
  - Getting started
  - Single Objective
    Single Objective
    
    0-1 Knapsack
  - Multiple Objectives
    Multiple Objectives
    
    0-1 Knapsack
    
    MOO minicourse
- Makefile
  Makefile
  - Introduction
  - Write a simple Makefile
  - Execute Makefile Execute Makefile
    Table of contents
    
    make with different Makefile name
  - Learn more about Makefile
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Table of contents

make with different Makefile name

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