Khanh's Research Group @ Univ. of Aizu

Introduction

🏠 Home
ℹ️ Information
ℹ️ Information
- 🌐 About this website
- 🔰 Guidance for new student (AY 2025)
- 🔰 Checklist for new student orientation meeting
  🔰 Checklist for new student orientation meeting
- 🚂 Training for new members
  🚂 Training for new members
- 🔬 Server/Page Info
  🔬 Server/Page Info
- 📑 Paper submission
  📑 Paper submission
- 🎓 Graduation Thesis
  🎓 Graduation Thesis
  - Preparation
  - After the presentation
👨‍🏫 Invited Talks
👨‍🏫 Invited Talks
📅 Meetings
📅 Meetings
🗂️ Tutorial
🗂️ Tutorial
- List of tutorials
- 🛠 HW Design
  🛠 HW Design
  - Verilog/SystemVerilog/VHDL tutorial
    Verilog/SystemVerilog/VHDL tutorial
    
    Intro
    
    Combinational Logic
    
    Sequential Logic
    
    Reset and Clock
    
    Naming
    
    RTL template
    
    Testbench template
    
    Useful website
    Useful website
    
    Asic-world
    
    Stitt-hub
    
    RTL-Training Repo
  - Simulate with Modelsim
    Simulate with Modelsim
    
    Introduction
    
    Clone the project
    
    Source the env variables
    
    Write your Verilog code
    
    Open Modelsim
    
    Use command line
    
    Code Coverage
    
    Write a script
    
    Learn More!
  - ASIC
    ASIC
    
    Basic
    Basic
    
    Getting started
    
    Writing Verilog
    
    RTL Simulation
    
    Synthesis (Synopsys DC)
    
    Place and Route
    
    Mini Ex
    
    Advanced
    Advanced
    
    Getting started
    
    Explore the library
    
    Post-synthesis simulation
    
    Post-synthesis simulation with timing
    
    Post-place-and-route sim
    
    Macro
    
    Through-Silicon-Via (TSV)
    
    OpenRAM
    
    Power estimation
    
    Clock-gating
    
    Temperature simulation
    
    Design: 🕸️ Network-on-Chip
    Design: 🕸️ Network-on-Chip
    
    Getting started
    
    Simulation
    
    SNN Simulation
    
    Synthesis
    
    Post-synthesis Simulation
    
    Place and Route
    
    Power estimation
    
    Sample projects
  - FPGA
    FPGA
    
    Basic
    Basic
    
    0. Installation
    
    Standalone RTL design
    Standalone RTL design
    
    1. Create a project
    
    2. Run the project on FPGA
    
    3. Understand the reports
    
    Simple SoC
    Simple SoC
    
    1. Create a project
    
    2. Port to SDK
    
    3. Run the program in the FPGA
    
    Custom IP
    Custom IP
    
    Introduction + Materials
    
    General Instruction
    
    Lab-1
    
    Lab-2
    
    Lab-3
    
    Lab-4
    
    Lab-5
    
    Sample Projects
    Sample Projects
    
    SNN on Basys 3
    
    SNN on Arty 7
    
    LIF neuron on MicroZed
- 🤖 Machine Learning
  🤖 Machine Learning
  - Getting started
  - General Machine Learning
    General Machine Learning
    
    Getting started
    
    Installation
    
    Dataset
    
    Notable techniques and Recommendation
  - Artificial Neural Network
  - Spiking Neural Network
    Spiking Neural Network
    
    Introduction
    
    Neurons
    
    Neurons
    
    Neuron
    
    Izhikevich
    
    SNNTorch
    SNNTorch
    
    Official tutorial
    
    Bindsnet
    Bindsnet
    
    STDP learning
    
    Spiking Jelly
    Spiking Jelly
    
    1.1 Time-step
    
    1.2 Using neuron
    
    1.3 Input size and net reset
    
    3.1 Revisit LIF neuron
    
    3.2 Revisit LIF neuron part 2
    
    3.3 Design your neuron
- Accessing servers
  Accessing servers
- 🎯 Optimization
  🎯 Optimization
  - Getting started
  - Single Objective
    Single Objective
    
    0-1 Knapsack
  - Multiple Objectives
    Multiple Objectives
    
    0-1 Knapsack
    
    MOO minicourse
- Makefile
  Makefile
- Git
  Git
  - Intro
  - Basic
  - Advanced
  - Branch
- Markdown
  Markdown
  - Intro
  - Basic
  - Advanced
♾️ Member
♾️ Member
- Faculty Advisor
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- Graduate
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  Undergraduate
- Exchange Student
  Exchange Student
  - AY2024
    
    AY2024
- Alumni
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  - AY2023
    
    AY2023
    
    NGUYEN Ngo Doanh
  - AY2024
    
    AY2024
    
    SHIOTA Rui
    
    KOBAYASHI Ryoji
    
    HANYU Yuga
🎗️ Management
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- 🔒 Password Protected
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- 📚 Books
- 🌐 Website
- 🖥 Server: how-to
- ⚗️ Materials
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- 🈸 University Docs
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🖼️ Moments
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- Archive
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- Categories
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🎟️ Events
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🛂 Join Us
🛂 Join Us
- For undergraduate students
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- Scholarships
- TA/RA/Part-time Positions
- How to write a research plan
- How we work
- What you learn
- GT themes (for B2 students)
  GT themes (for B2 students)
  - AY2025
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- Alumni Voices
🌐 Links
🌐 Links
- 📝 The Thinking Circuit
- 🚧 Project
  🚧 Project
  - Torch2HW
  - 🎓 Available GT Topics (2024)
- 🌐 Useful link
- ↗️ Github
- ▶️ YouTube
📩 Contact

2vSaMTvYEExfoF4rqKxEYQ==;A3387y8ft/A1sUpUVY8wAa61MBaUJgfRQblVLWTLRC83V5Ulc4iZz8qfIIZjVJhFKJi1ahlILRj7aD+9JaaGb1B42Sv6EmRgifWssEeucTZ8LXKODFaGTROYbvgj+/XMPG3o41PHtJVUzTE135Wk99Qf6lbihpTIn9p9Uf1VFYVWSTg1ojHW5g+Bv/jz5oZllmxfcZALFEXRLe8NpdldS8w+STW3RtakgnUamSeJx3NgSKs6G/JVEP0XwC8sW7pOvIklAGW6tKdKon/ffRgJW4NrU/s0vow8NzBpkdqrInJyGWrXZbI1h8S/RTMQPxJlsRi7i/qM4Mps8sIGj46sf7Cwj4saHmMe+bKG8gRosazItQpG99ymuMkikVUcvMfrFKLhoJdQ3TSvZSXbHe8aZRp1sPD+aFZfaw5VZIleKgMG8lk35L1RjCLTJYtMqhbNRRJB27xnm/WpcZquUQZfQ2jzimirLabjf84FrosYDNQljNczK0bQ/iHlaCFYKYdrXWntBPD7+ICpMwqwHI4qBxifzayDtKhXaqP2IAHRMK70B98YQonDK2xFIiYG7kWf8UfCn9FsA3u0Yxeex3BOd2WdQdyMD/z3obIIavL6aM0QpBiOlHmQlH4MOMeguT6j30faKDFCZ86OpS3mJgB0JTDAI3g2Rw8jEfESxV53Y7ao/bkto8rJTKh3tjUgWz6QFBsSvQKTnKlQCCqgLPLf5ygBUtq8abTdwa/g4Uz3sssgRVDYa9F+Rq1BMgoXUL/Xp8M3gMO4rnYr6+tvFHvAAqbqnGk6kwLkgk5Sxaq4t0ZSz/rYF+mw/Nzig+zyPJNoKSTnvQWADGsDcPgYBaBhD3dv/0haHCx1EVng+woT1KtmjZdgiXpON0HeB+nJEuuB+HJD/owvv2chQ/JuQbWmSn8tF+Vu7BkkqwqKWus6fBwkt2iZEZzZO0x3TXZqSWwkH7DNKlBg7/Gs9qjhBU0Cjw6yz8Lx+V/LzUcvki/acW6Jy3IlaR0VYoNYZywpAZwmueMfbpbYolT/PPaeT9DCn2X6yV3+b35DJ1gj5DhJvq2yh/lT/xujY3f6aBl/dZdOMTaWQHdyyatso6toIvYlxEkl5pz6GI//kjL1jLDWTg8XKJF5Ewx4XqcWXeww4/JG/E2PV7GpwfXUPu3kHNGQzJyjo7a/mTJ1pZOADYxCeTctS2LsIo53gOPTPonOqO1Fp0vZA4YTZFVAkwmW1MqVF8PXG1zBG7eCN47HLqqs3z0DTq5y3eM9mmF8omgcp/2bPaxwf7JjgS8F0i+AGgkuIxAXSoKvXH9rkKx/NazIOZF32OMleKpQ8yf/uqywDnuWNF5wddTjX7r4l7KQAvcKNbm0YAbAG2/zjaZlAy9HhWhT2A3F8wv0+0ovltmpM5TeQITJdggVafaJuRoPGgxOCscmUpJZ4JnkWyph+ECBQo8M5mMivh0RLztHlU1hqCwK9VbwmX1YQoTBViP9NNthAjmSb8vvmabX7jVgZhz4i4xX3fuSrITJwMMC9YBAi0xMJRe3aoPwHmAGiSFd2dqWwiubddSRKW3cy3fxhF/jlq9LW3Qx9QIkOjvbywMcBkDtrqh40/08P+5zyHjjP1irfmMsdi1QTWY8vFRmUuSfrwzE15QG2jq9bL4GuNDg9UUt4/nH3SbRVYerIdESphApTcqVB+sXw8dDOxU8wCPCttpvZ9e8KcgD6W8JCv+Gzj4eZ/Ys7aR29l7VNluAlVlBgg==

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