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    Verilog/SystemVerilog/VHDL tutorial
    
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  - Simulate with Modelsim
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    Clone the project
    
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  - ASIC
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    Design: 🕸️ Network-on-Chip
    Design: 🕸️ Network-on-Chip
    
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  - FPGA
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    Basic
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    0. Installation
    
    Standalone RTL design
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    1. Create a project
    
    2. Run the project on FPGA
    
    3. Understand the reports
    
    Simple SoC
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    1. Create a project
    
    2. Port to SDK
    
    3. Run the program in the FPGA
    
    Custom IP
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    LIF neuron on MicroZed
- 🤖 Machine Learning
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  - Spiking Neural Network
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    Izhikevich
    
    SNNTorch
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    Official tutorial
    
    Bindsnet
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    STDP learning
    
    Spiking Jelly
    Spiking Jelly
    
    1.1 Time-step
    
    1.2 Using neuron
    
    1.3 Input size and net reset
    
    3.1 Revisit LIF neuron
    
    3.2 Revisit LIF neuron part 2
    
    3.3 Design your neuron
- Accessing servers
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- 🎯 Optimization
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