Khanh's Research Group @ Univ. of Aizu

Write your Verilog code

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  - Verilog/SystemVerilog/VHDL tutorial
    Verilog/SystemVerilog/VHDL tutorial
    
    Intro
    
    Combinational Logic
    
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    Reset and Clock
    
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  - Simulate with Modelsim
    Simulate with Modelsim
    
    Introduction
    
    Clone the project
    
    Source the env variables
    
    Write your Verilog code Write your Verilog code
    Table of contents
    
    Write the example Flip Flop
    
    Write a Testbench
    
    Open Modelsim
    
    Use command line
    
    Code Coverage
    
    Write a script
    
    Learn More!
  - ASIC
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    Mini Ex
    
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    Design: 🕸️ Network-on-Chip
    Design: 🕸️ Network-on-Chip
    
    Getting started
    
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  - FPGA
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    0. Installation
    
    Standalone RTL design
    Standalone RTL design
    
    1. Create a project
    
    2. Run the project on FPGA
    
    3. Understand the reports
    
    Simple SoC
    Simple SoC
    
    1. Create a project
    
    2. Port to SDK
    
    3. Run the program in the FPGA
    
    Custom IP
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    SNN on Basys 3
    
    SNN on Arty 7
    
    LIF neuron on MicroZed
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  - Artificial Neural Network
  - Spiking Neural Network
    Spiking Neural Network
    
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    Neuron
    
    Izhikevich
    
    SNNTorch
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    Official tutorial
    
    Bindsnet
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    Spiking Jelly
    Spiking Jelly
    
    1.1 Time-step
    
    1.2 Using neuron
    
    1.3 Input size and net reset
    
    3.1 Revisit LIF neuron
    
    3.2 Revisit LIF neuron part 2
    
    3.3 Design your neuron
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Table of contents

Write the example Flip Flop
Write a Testbench

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